在verilog语法中的reg到底对应的是什么触发器,为什么在组合逻辑中也使用了reg却没有时钟信号?
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发布时间:2022-05-01 01:21
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热心网友
时间:2023-10-08 23:46
reg是d触发器。
组合逻辑电路本来就跟时钟没有关系,一般组合逻辑的输出用wire定义,线网类型。追问通常D触发器都是带有时钟clk的,是上升沿触发,reg用在组合逻辑里边却没有时钟,怎么解释?
热心网友
时间:2023-10-08 23:46
verilog-2001标准中对reg的规定如下
“Assignments to a reg are made by proceral assignments (see 6.2 and 9.2). Since the reg holds a value between assignments, it can be used to model hardware registers. Edge-sensitive (i.e., flip-flops) and level sensitive (i.e., RS and transparent latches) storage elements can be modeled. A reg needs not represent a hardware storage element since it can also be used to represent combinatorial logic.”