分频系数可变的分频器verilog代码怎么写?
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发布时间：2022-04-24 12:31
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热心网友
时间：2022-05-03 08:06
追答mole fredivider(clk,rst,clk_out);
input clk,rst;
output reg clk_out;
reg [31:0] counter;
always @(posedege clk or negedge rst)
begin
if(!rst)
begin
counter<=32'd0;
clk_out <= 1'b0;
end
else
if(counter==32'd25000) // 25000 换成 (1/f_out)/(1/f_in)/2
begin
counter<=32'd0;
clk_out <= ~clk_out;
end
else
begin
counter<=counter+1;
end
end
endmole
